PIC16LF18854 Datasheet, PDF (240/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE⁽¹⁾
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
PORTE
TRISE
—
—
—
—
RE3
RE2
RE1
RE0
225
—
—
—
—
—⁽¹⁾
TRISE2 TRISE1 TRISE0
225
LATE
—
—
—
—
—
LATE2
LATE1
LATE0
226
ANSELE
—
—
—
—
—
ANSE2
ANSE1
ANSE0
226
WPUE
—
—
—
—
WPUE3 WPUE2 WPUE1 WPUE0
227
ODCONE
—
—
—
—
—
ODCE2 ODCE1 ODCE0
227
SLRCONE
—
—
—
—
—
SLRE2
SLRE1
SLRE0
228
INLVLE
—
—
—
—
INLVLE3 INLVLE2 INLVLE1 INLVLE0
228
CCDPE
—
—
—
—
—
CCDPE2 CCDPE1 CCDPE0
229
CCDNE
—
—
—
—
—
CCDNE2 CCDNE1 CCDNE0
229
CCDCON
CCDEN
―
―
―
―
―
CCDS<1:0>
199
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.
Note 1: Unimplemented, read as ‘1’.
TABLE 12-9: SUMMARY OF CONFIGURATION WORD WITH PORTE
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1
13:8
CONFIG2
7:0
—
—
BOREN<1:0>
DEBUG STVREN PPS1WAY ZCDDIS BORV
LPBOREN —
—
—
PWRTE
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE.
Bit 8/0
—
MCLRE
Register
on Page
92
DS40001824A-page 240
Preliminary
 2016 Microchip Technology Inc.