PIC16LF18854 Datasheet, PDF (189/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
11.10.1 BURST MODE
When MODE = 01, the scanner is in Burst mode. In
Burst mode, CPU operation is stalled beginning with the
operation after the one that sets the SCANGO bit, and
the scan begins, using the instruction clock to execute.
The CPU is held until the scan stops. Note that because
the CPU is not executing instructions, the SCANGO bit
cannot be cleared in software, so the CPU will remain
stalled until one of the hardware end-conditions occurs.
Burst mode has the highest throughput for the scanner,
but has the cost of stalling other execution while it
occurs.
11.10.2 CONCURRENT MODE
When MODE = 00, the scanner is in Concurrent mode.
Concurrent mode, like Burst mode, stalls the CPU
while performing accesses of memory. However, while
Burst mode stalls until all accesses are complete,
Concurrent mode allows the CPU to execute in
between access cycles.
11.10.3 TRIGGERED MODE
When MODE = 11, the scanner is in Triggered mode.
Triggered mode behaves identically to Concurrent
mode, except instead of beginning the scan
immediately upon the SCANGO bit being set, it waits
for a rising edge from a separate trigger clock, the
source of which is determined by the SCANTRIG
register.
11.10.4 PEEK MODE
When MODE = 10, the scanner is in Peek mode. Peek
mode waits for an instruction cycle in which the CPU
does not need to access the NVM (such as a branch
instruction) and uses that cycle to do its own NVM
access. This results in the lowest throughput for the NVM
access (and can take a much longer time to complete a
scan than the other modes), but does so without any
impact on execution times, unlike the other modes.
TABLE 11-1: SUMMARY OF SCANNER MODES
MODE<1:0>
First Scan Access
Description
CPU Operation
11 Triggered
10 Peek
As soon as possible
following a trigger
At the first dead cycle
01 Burst
As soon as possible
00 Concurrent
Stalled during NVM access
Timing is unaffected
Stalled during NVM access
CPU resumes execution following
each access
CPU continues execution following
each access
CPU suspended until scan
completes
CPU resumes execution following
each access
11.10.5 INTERRUPT INTERACTION
The INTM bit of the SCANCON0 register controls the
scanner’s response to interrupts depending on which
mode the NVM scanner is in, as described in
Table 11-2.
TABLE 11-2:
INTM
1
0
SCAN INTERRUPT MODES
MODE<1:0>
MODE == Burst
MODE != Burst
Interrupt overrides SCANGO to pause the burst
and the interrupt handler executes at full speed;
Scanner Burst resumes when interrupt
completes.
Interrupts do not override SCANGO, and the
scan (burst) operation will continue; interrupt
response will be delayed until scan completes
(latency will be increased).
Scanner suspended during interrupt response;
interrupt executes at full speed and scan
resumes when the interrupt is complete.
Scanner accesses NVM during interrupt
response. If MODE != Peak the interrupt handler
execution speed will be affected.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 189