PIC16LF18854 Datasheet, PDF (575/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 33-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0/0
SPEN⁽¹⁾
bit 7
R/W-0/0
RX9
R/W-0/0
SREN
R/W-0/0
CREN
R/W-0/0
ADDEN
R-0/0
FERR
R-0/0
OERR
R-0/0
RX9D
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SPEN: Serial Port Enable bit⁽¹⁾
1 = Serial port enabled
0 = Serial port disabled (held in Reset)
bit 6
RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit
Asynchronous mode:
Unused in this mode – value ignored
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Unused in this mode – value ignored
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection – enable interrupt and load of the receive buffer when the ninth bit in
the receive buffer is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Unused in this mode – value ignored
bit 2
FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
Note 1: The EUSART module automatically changes the pin from tri-state to drive as needed. Configure the
associated TRIS bits for TX/CK and RX/DT to 1.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 575