PIC16LF18854 Datasheet, PDF (155/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
8.2.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source, with the exception of the clock
switch interrupt, has both its interrupt enable bit and
interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
- SLEEP instruction will execute as a NOP
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared
• If the interrupt occurs during or after the
execution of a SLEEP instruction
- SLEEP instruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 8-2:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
CLKIN⁽¹⁾
CLKOUT⁽²⁾
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST⁽³⁾
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
PC
Instruction
Fetched
Inst(PC) = Sleep
Instruction
Executed
Inst(PC - 1)
Processor in
Sleep
PC + 1
Inst(PC + 1)
Sleep
PC + 2
Interrupt Latency⁽⁴⁾
PC + 2
Inst(PC + 2)
Inst(PC + 1)
PC + 2
Forced NOP
0004h
Inst(0004h)
Forced NOP
0005h
Inst(0005h)
Inst(0004h)
Note 1:
2:
3:
4:
External clock. High, Medium, Low mode assumed.
CLKOUT is shown here for timing reference.
TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
8.2.3 LOW-POWER SLEEP MODE
The PIC16F18855/75 device contains an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode.
The PIC16F18855/75 allows the user to optimize the
operating current in Sleep, depending on the
application requirements.
Low-Power Sleep mode can be selected by setting the
VREGPM bit of the VREGCON register. Depending on
the configuration of these bits, the LDO and reference
circuitry are placed in a low-power state when the
device is in Sleep.
8.2.3.1 Sleep Current vs. Wake-up Time
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking-up from Sleep, an extra delay time
is required for these circuits to return to the normal
configuration and stabilize.
The Low-Power Sleep mode is beneficial for
applications that stay in Sleep mode for long periods of
time. The Normal mode is beneficial for applications
that need to wake from Sleep quickly and frequently.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 155