PIC16LF18854 Datasheet, PDF (171/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
10.4.2 NVM UNLOCK SEQUENCE
The unlock sequence is a mechanism that protects the
NVM from unintended self-write programming or
erasing. The sequence must be executed and
completed without interruption to successfully
complete any of the following operations:
• PFM Row Erase
• Load of PFM write latches
• Write of PFM write latches to PFM memory
• Write of PFM write latches to User IDs
• Write to EEPROM
The unlock sequence consists of the following steps
and must be completed in order:
• Write 55h to NVMCON2
• Write AAh to NMVCON2
• Set the WR bit of NVMCON1
Once the WR bit is set, the processor will stall internal
operations until the operation is complete and then
resume with the next instruction.
Note:
The two NOP instructions after setting the
WR bit that were required in previous
devices are not required for
PIC16(L)F18856/76 devices. See
Figure 10-2.
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
FIGURE 10-2:
NVM UNLOCK
SEQUENCE FLOWCHART
Rev. 10-000047B
8/24/2015
Start
Unlock Sequence
Write 0x55 to
NVMCON2
Write 0xAA to
NVMCON2
Initiate
Write or Erase operation
(WR = 1)
End
Unlock Sequence
EXAMPLE 10-2: NVM UNLOCK SEQUENCE
BCF
BANKSEL
BSF
MOVLW
INTCON, GIE
NVMCON1
NVMCON1, WREN
55h
; Recommended so sequence is not interrupted
;
; Enable write/erase
; Load 55h
MOVWF
MOVLW
MOVWF
BSF
BSF
NVMCON2
AAh
NVMCON2
NVMCON1, WR
INTCON, GIE
; Step 1: Load 55h into NVMCON2
; Step 2: Load W with AAh
; Step 3: Load AAH into NVMCON2
; Step 4: Set WR bit to begin write/erase
; Re-enable interrupts
Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown.
2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.
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Preliminary
DS40001824A-page 171