PIC16LF18854 Datasheet, PDF (379/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
24.2 FIXED DUTY CYCLE MODE
In Fixed Duty Cycle (FDC) mode, every time the
accumulator overflows (NCO_overflow), the output is
toggled. This provides a 50% duty cycle, provided that
the increment value remains constant. For more
information, see Figure 24-2.
The FDC mode is selected by clearing the N1PFM bit
in the NCO1CON register.
24.3 PULSE FREQUENCY MODE
In Pulse Frequency (PF) mode, every time the
Accumulator overflows, the output becomes active for
one or more clock periods. Once the clock period
expires, the output returns to an inactive state. This
provides a pulsed output. The output becomes active
on the rising clock edge immediately following the
overflow event. For more information, see Figure 24-2.
The value of the active and inactive states depends on
the polarity bit, N1POL in the NCO1CON register.
The PF mode is selected by setting the N1PFM bit in
the NCO1CON register.
24.3.1 OUTPUT PULSE WIDTH CONTROL
When operating in PF mode, the active state of the out-
put can vary in width by multiple clock periods. Various
pulse widths are selected with the N1PWS<2:0> bits in
the NCO1CLK register.
When the selected pulse width is greater than the
Accumulator overflow time frame, then DDS operation
is undefined.
24.4 OUTPUT POLARITY CONTROL
The last stage in the NCO module is the output polarity.
The N1POL bit in the NCO1CON register selects the
output polarity. Changing the polarity while the
interrupts are enabled will cause an interrupt for the
resulting output transition.
The NCO output signal is available to the following
peripherals:
• CLC
• CWG
• Timer1/3/5
• Timer2/4/6
• SMT
• DSM
• Reference Clock Output
24.5 Interrupts
When the accumulator overflows (NCO_overflow), the
NCO Interrupt Flag bit, NCO1IF, of the PIR7 register is
set. To enable the interrupt event (NCO_interrupt), the
following bits must be set:
• N1EN bit of the NCO1CON register
• NCO1IE bit of the PIE7 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt must be cleared by software by clearing
the NCO1IF bit in the Interrupt Service Routine.
24.6 Effects of a Reset
All of the NCO registers are cleared to zero as the
result of a Reset.
24.7 Operation in Sleep
The NCO module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock source selected remains active.
The HFINTOSC remains active during Sleep when the
NCO module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the NCO clock
source, when the NCO is enabled, the CPU will go idle
during Sleep, but the NCO will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 379