PIC16LF18854 Datasheet, PDF (625/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
FIGURE 37-14: CLC PROPAGATION TIMING
CLCxINn
CLC
Input time
LCx_in[n]⁽¹⁾
CLC
Module
LCx_out⁽¹⁾
CLC
Output time
Rev. 10-000031A
7/30/2013
CLCx
CLCxINn
CLC
Input time
LCx_in[n]⁽¹⁾
CLC
Module
CLC01
CLC02
Note 1: See Figure 22-1 to identify specific CLC signals.
LCx_out⁽¹⁾
CLC
Output time
CLC03
CLCx
TABLE 37-20: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param.
No.
Sym.
Characteristic
Min. Typ† Max. Units
Conditions
CLC01* TCLCIN CLC input time
—
7 OS17 ns (Note 1)
CLC02* TCLC CLC module input to output progagation time
—
24
—
12
— ns VDD = 1.8V
— ns VDD > 3.6V
CLC03* TCLCOUT CLC output time
Rise Time — OS18 — — (Note 1)
Fall Time — OS19 — — (Note 1)
CLC04* FCLCMAX CLC maximum switching frequency
—
32 FOSC MHz
*
†
Note 1:
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
See Table 37-10 for OS17, OS18 and OS19 rise and fall times.
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Preliminary
DS40001824A-page 625