PIC16LF18854 Datasheet, PDF (585/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 34-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CLKREN
—
—
CLKRDC<1:0>
CLKRDIV<2:0>
bit 7
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6-5
bit 4-3
bit 2-0
Note 1:
CLKREN: Reference Clock Module Enable bit
1 = Reference Clock module enabled
0 = Reference Clock module is disabled
Unimplemented: Read as ‘0’
CLKRDC<1:0>: Reference Clock Duty Cycle bits ⁽¹⁾
11 = Clock outputs duty cycle of 75%
10 = Clock outputs duty cycle of 50%
01 = Clock outputs duty cycle of 25%
00 = Clock outputs duty cycle of 0%
CLKRDIV<2:0>: Reference Clock Divider bits
111 = FOSC divided by 128
110 = FOSC divided by 64
101 = FOSC divided by 32
100 = FOSC divided by 16
011 = FOSC divided by 8
010 = FOSC divided by 4
001 = FOSC divided by 2
000 = FOSC
Bits are valid for Reference Clock divider values of two or larger, the base clock cannot be further divided.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 585