PIC16LF18854 Datasheet, PDF (142/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-11: PIR0: PERIPHERAL INTERRUPT STATUS REGISTER 0
U-0
U-0
R/W/HS-0/0
R-0
U-0
U-0
U-0
R/W/HS-0/0
—
—
TMR0IF
IOCIF
—
—
—
INTF⁽¹⁾
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS= Hardware Set
bit 7-6
bit 5
bit 4
bit 3-1
bit 0
Unimplemented: Read as ‘0’
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
IOCIF: Interrupt-on-Change Interrupt Flag bit (read-only)⁽²⁾
1 = One or more of the IOCAF-IOCEF register bits are currently set, indicating an enabled edge was
detected by the IOC module.
0 = None of the IOCAF-IOCEF register bits are currently set
Unimplemented: Read as ‘0’
INTF: INT External Interrupt Flag bit⁽¹⁾
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur
Note 1: The External Interrupt GPIO pin is selected by INTPPS (Register 13-1).
2: The IOCIF bits are the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag,
application firmware should clear all of the lower level IOCAF-IOCEF register bits.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
DS40001824A-page 142
Preliminary
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