PIC16LF18854 Datasheet, PDF (65/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3-13: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on all
other Resets
Bank 14
CPU CORE REGISTERS; see Table 3-2 for specifics
70Ch
PIR0
—
—
TMR0IF
IOCIF
—
—
—
70Dh
PIR1
OSFIF
CSWIF
—
—
—
—
ADTIF
70Eh
PIR2
—
ZCDIF
—
—
—
—
C2IF
70Fh
PIR3
—
—
RCIF
TXIF
BCL2IF
SSP2IF
BCL1IF
710h
PIR4
—
—
TMR6IF
TMR5IF
TMR4IF
TMR3IF
TMR2IF
711h
PIR5
CLC4IF
CLC3IF
CLC2IF
CLC1IF
—
TMR5GIF
TMR3GIF
712h
PIR6
—
—
—
CCP5IF
CCP4IF
CCP3IF
CCP2IF
713h
PIR7
SCANIF
CRCIF
NVMIF
NCO1IF
—
CWG3IF
CWG2IF
714h
PIR8
—
—
SMT2PWAIF SMT2PRAIF
SMT2IF
SMT1PWAIF
SMT1PRAIF
715h
—
—
Unimplemented
716h
PIE0
—
—
TMR0IE
IOCIE
—
—
—
717h
PIE1
OSFIE
CSWIE
—
—
—
—
ADTIE
718h
PIE2
—
ZCDIE
—
—
—
—
C2IE
719h
PIE3
—
—
RCIE
TXIE
BCL2IE
SSP2IE
BCL1IE
71Ah
PIE4
—
—
TMR6IE
TMR5IE
TMR4IE
TMR3IE
TMR2IE
71Bh
PIE5
CLC4IE
CLC3IE
CLC2IE
CLC1IE
—
TMR5GIE
TMR3GIE
71Ch
PIE6
—
—
—
CCP5IE
CCP4IE
CCP3IE
CCP2IE
71Dh
PIE7
SCANIE
CRCIE
NVMIE
NCO1IE
—
CWG3IE
CWG2IE
71Eh
PIE8
—
—
SMT2PWAIE SMT2PRAIE
SMT2IE
SMT1PWAIE
SMT1PRAIE
71Fh
—
—
Unimplemented
Legend:
Note 1:
2:
x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Register present on PIC16F18855/75 devices only.
Unimplemented, read as ‘1’.
INTF
ADIF
C1IF
SSP1IF
TMR1IF
TMR1GIF
CCP1IF
CWG1IF
SMT1IF
INTE
ADIE
C1IE
SSP1IE
TMR1IE
TMR1GIE
CCP1IE
CWG1IE
SMT1IE
--00 ---0
00-- --00
-0-- --00
--00 0000
--00 0000
0000 -000
---0 0000
0000 -000
--00 0000
—
--00 ---0
00-- --00
-0-- --00
--00 0000
--00 0000
0000 -000
---0 0000
0000 -000
--00 0000
—
--00 ---0
00-- --00
-0-- --00
--00 0000
--00 0000
0000 -000
---0 0000
0000 -000
--00 0000
—
--00 ---0
00-- --00
-0-- --00
--00 0000
--00 0000
0000 -000
---0 0000
0000 -000
--00 0000
—