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PIC16LF18854 Datasheet, PDF (153/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture
PIC16(L)F18856/76
8.0 POWER-SAVING OPERATION
MODES
The purpose of the Power-Down modes is to reduce
power consumption. There are two Power-Down
modes: DOZE mode and Sleep mode.
8.1 DOZE Mode
DOZE mode allows for power saving by reducing CPU
operation and program memory (PFM) access, without
affecting peripheral operation. DOZE mode differs from
Sleep mode because the system oscillators continue to
operate, while only the CPU and PFM are affected. The
reduced execution saves power by eliminating
unnecessary operations within the CPU and memory.
When the Doze Enable (DOZEN) bit is set (DOZEN =
1), the CPU executes only one instruction cycle out of
every N cycles as defined by the DOZE<2:0> bits of the
CPUDOZE register. For example, if DOZE<2:0> = 100,
the instruction cycle ratio is 1:32. The CPU and
memory execute for one instruction cycle and then lay
idle for 31 instruction cycles. During the unused cycles,
the peripherals continue to operate at the system clock
speed.
FIGURE 8-1:
DOZE MODE OPERATION EXAMPLE
System
Clock
1
1
1
1
1
1
1
1
1
1
1
1
1
/ŶƐƚƌƵĐƚŝŽŶ
WĞƌŝŽĚ
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
CPU Clock
PFM Op’s
1234
Fetch
1234
Fetch
12341234123412341234
Push
0004h
Fetch
Fetch
CPU Op’s
Exec
Exec
Exec(1,2)
NOP
Exec
Exec
Exec
I nter rup t
Here
(ROI = 1)
Note 1: Multi-cycle instructions are executed to completion before fetching 0004h.
2: If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.
8.1.1 DOZE OPERATION
The Doze operation is illustrated in Figure 8-1. For this
example:
• Doze enable (DOZEN) bit set (DOZEN = 1)
• DOZE<2:0> = 001 (1:4) ratio
• Recover-on-Interrupt (ROI) bit set (ROI = 1)
As with normal operation, the PFM fetches for the next
instruction cycle. The Q-clocks to the peripherals
continue throughout.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 153