PIC16LF18854 Datasheet, PDF (188/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
11.7 Configuring the CRC
The following steps illustrate how to properly configure
the CRC.
1. Determine if the automatic Program Memory
scan will be used with the scanner or manual
calculation through the SFR interface and per-
form the actions specified in Section 11.4 “CRC
Data Sources”, depending on which decision
was made.
2. If desired, seed a starting CRC value into the
CRCACCH/L registers.
3. Program the CRCXORH/L registers with the
desired generator polynomial.
4. Program the DLEN<3:0> bits of the CRCCON1
register with the length of the data word – 1
(refer to Example 11-1). This determines how
many times the shifter will shift into the accumu-
lator for each data word.
5. Program the PLEN<3:0> bits of the CRCCON1
register with the length of the polynomial – 2
(refer to Example 11-1).
6. Determine whether shifting in trailing zeros is
desired and set the ACCM bit of CRCCON0
register appropriately.
7. Likewise, determine whether the MSb or LSb
should be shifted first and write the SHIFTM bit
of CRCCON0 register appropriately.
8. Write the CRCGO bit of the CRCCON0 register
to begin the shifting process.
9a. If manual SFR entry is used, monitor the FULL bit
of CRCCON0 register. When FULL = 0, another
word of data can be written to the CRCDATH/L
registers, keeping in mind that CRCDATH should
be written first if the data has >8 bits, as the
shifter will begin upon the CRCDATL register
being written.
9b. If the scanner is used, the scanner will
automatically stuff words into the CRCDATH/L
registers as needed, as long as the SCANGO bit
is set.
10a.If using the Flash memory scanner, monitor the
SCANIF (or the SCANGO bit) for the scanner to
finish pushing information into the CRCDATA
registers. After the scanner is completed, moni-
tor the CRCIF (or the BUSY bit) to determine
that the CRC has been completed and the check
value can be read from the CRCACC registers.
If both the interrupt flags are set (or both BUSY
and SCANGO bits are cleared), the completed
CRC calculation can be read from the
CRCACCH/L registers.
10b.If manual entry is used, monitor the CRCIF (or
BUSY bit) to determine when the CRCACC
registers will hold the check value.
11.8 Program Memory Scan
Configuration
If desired, the Program Memory Scan module may be
used in conjunction with the CRC module to perform a
CRC calculation over a range of program memory
addresses. In order to set up the Scanner to work with
the CRC you need to perform the following steps:
1. Set the EN bit to enable the module. This can be
performed at any point preceding the setting of
the SCANGO bit, but if it gets disabled, all
internal states of the Scanner are reset
(registers are unaffected).
2. Choose which memory access mode is to be
used (see Section 11.10 “Scanning Modes”)
and set the MODE bits of the SCANCON0
register appropriately.
3. Based on the memory access mode, set the
INTM bits of the SCANCON0 register to the
appropriate interrupt mode (see Section
11.10.5 “Interrupt Interaction”)
4. Set the SCANLADRL/H and SCANHADRL/H
registers with the beginning and ending
locations in memory that are to be scanned.
5. Begin the scan by setting the SCANGO bit in the
SCANCON0 register. The scanner will wait
(CRCGO must be set) for the signal from the
CRC that it is ready for the first Flash memory
location, then begin loading data into the CRC.
It will continue to do so until it either hits the
configured end address or an address that is
unimplemented on the device, at which point the
SCANGO bit will clear, Scanner functions will
cease, and the SCANIF interrupt will be
triggered. Alternately, the SCANGO bit can be
cleared in software if desired.
11.9 Scanner Interrupt
The scanner will trigger an interrupt when the
SCANGO bit transitions from ‘1’ to ‘0’. The SCANIF
interrupt flag of PIR7 is set when the last memory
location is reached and the data is entered into the
CRCDATA registers. The SCANIF bit can only be
cleared in software. The SCAN interrupt enable is the
SCANIE bit of the PIE7 register.
11.10 Scanning Modes
The memory scanner can scan in four modes: Burst,
Peek, Concurrent, and Triggered. These modes are
controlled by the MODE bits of the SCANCON0
register. The four modes are summarized in Table 11-1.
DS40001824A-page 188
Preliminary
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