PIC16LF18854 Datasheet, PDF (301/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
20.9 CWG Steering Mode
In Steering mode (MODE = 00x), the CWG allows any
combination of the CWGxx pins to be the modulated
signal. The same signal can be simultaneously avail-
able on multiple pins, or a fixed-value output can be
presented.
When the respective STRx bit of CWGxOCON0 is ‘0’,
the corresponding pin is held at the level defined. When
the respective STRx bit of CWGxOCON0 is ‘1’, the pin
is driven by the input data signal. The user can assign
the input data signal to one, two, three, or all four output
pins.
The POLx bits of the CWGxCON1 register control the
signal polarity only when STRx = 1.
The CWG auto-shutdown operation also applies in
Steering modes as described in Section 20.10 “Auto-
Shutdown”. An auto-shutdown event will only affect
pins that have STRx = 1.
20.9.1 STEERING SYNCHRONIZATION
Changing the MODE bits allows for two modes of steer-
ing, synchronous and asynchronous.
When MODE = 000, the steering event is asynchro-
nous and will happen at the end of the instruction that
writes to STRx (that is, immediately). In this case, the
output signal at the output pin may be an incomplete
waveform. This can be useful for immediately removing
a signal from the pin.
When MODE = 001, the steering update is synchro-
nous and occurs at the beginning of the next rising
edge of the input data signal. In this case, steering the
output on/off will always produce a complete waveform.
Figure 20-10 and Figure 20-11 illustrate the timing of
asynchronous and synchronous steering, respectively.
FIGURE 20-10:
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION
(MODE<2:0> = 000)
CWGx_data
(Rising and Falling Source)
STR<D:A>
Rising Event
CWGx<D:A>
OVR<D:A>
follows CWGx_data
OVR<D:A> Data
FIGURE 20-11:
EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION
(MODE<2:0> = 001)
CWGx_data
(Rising and Falling Source)
STR<D:A>
CWGx<D:A>
OVR<D:A> Data
follows CWGx_data
OVR<D:A> Data
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 301