PIC16LF18854 Datasheet, PDF (20/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
Name
RA5/ANA5/SS1⁽¹⁾/MDSRC⁽¹⁾/IOCA5
Function
RA5
Input
Type
TTL/ST
Output Type
CMOS/OD General purpose I/O.
Description
ANA5
SS1⁽¹⁾
MDSRC⁽¹⁾
AN
TTL/ST
TTL/ST
—
ADC Channel A5 input.
—
MSSP1 SPI slave select input.
—
Modulator Source input.
IOCA5
TTL/ST
—
Interrupt-on-change input.
RA6/ANA6/OSC2/CLKOUT/IOCA6
RA6
TTL/ST CMOS/OD General purpose I/O.
ANA6
AN
—
ADC Channel A6 input.
OSC2
—
XTAL
External Crystal/Resonator (LP, XT, HS modes) driver output.
CLKOUT
—
CMOS/OD FOSC/4 digital output (in non-crystal/resonator modes).
IOCA6
TTL/ST
—
Interrupt-on-change input.
RA7/ANA7/OSC1/CLKIN/IOCA7
RA7
TTL/ST CMOS/OD General purpose I/O.
ANA7
AN
—
ADC Channel A7 input.
OSC1
XTAL
—
External Crystal/Resonator (LP, XT, HS modes) driver input.
CLKIN
TTL/ST
—
External digital clock input.
RB0/ANB0/C2IN1+/ZCD/SS2⁽¹⁾/
CCP4⁽¹⁾/CWG1IN⁽¹⁾/INT⁽¹⁾/IOCB0
IOCA7
RB0
ANB0
TTL/ST
TTL/ST
AN
—
CMOS/OD
—
Interrupt-on-change input.
General purpose I/O.
ADC Channel B0 input.
C2IN1+
AN
—
Comparator positive input.
ZCD
SS2⁽¹⁾
CCP4⁽¹⁾
CWG1IN⁽¹⁾
INT⁽¹⁾
AN
TTL/ST
TTL/ST
TTL/ST
TTL/ST
AN
—
CMOS/OD
—
—
Zero-cross detect input pin (with constant current sink/source).
MSSP2 SPI slave select input.
Capture/compare/PWM4 (default input location for capture
function).
Complementary Waveform Generator 1 input.
External interrupt request input.
RB1/ANB1/C1IN3-/C2IN3-/SCL2^(3,4)/
SCK2⁽¹⁾/CWG2IN⁽¹⁾/IOCB1
IOCB0
RB1
ANB1
TTL/ST
TTL/ST
AN
—
CMOS/OD
—
Interrupt-on-change input.
General purpose I/O.
ADC Channel B1 input.
C1IN3-
AN
—
Comparator negative input.
C2IN3-
SCL2^(3,4)
SCK2⁽¹⁾
CWG2IN⁽¹⁾
AN
I²C/
SMBus
TTL/ST
TTL/ST
—
Comparator negative input.
OD
MSSP2 I²C clock input/output.
CMOS/OD
—
MSSP2 SPI serial clock (default input location, SCK2 is a PPS
remappable input and output).
Complementary Waveform Generator 2 input.
IOCB1
TTL/ST
—
Interrupt-on-change input.
Legend: AN = Analog input or output
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
OD = Open-Drain
I²C = Schmitt Trigger input with I²C
HV = High Voltage
XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I²C specific or SMBus input buffer thresholds.
DS40001824A-page 20
Preliminary
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