PIC16LF18854 Datasheet, PDF (358/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 23-2: ADCON1: ADC CONTROL REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
ADPPOL
ADIPEN
ADGPOL
—
—
—
bit 7
U-0
R/W-0/0
—
ADDSEN
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4-1
bit 0
ADDPOL: Precharge Polarity bit
If ADPRE>0x00:
ADPPOL
1
0
Action During 1st Precharge Stage
External (selected analog I/O pin)
Shorted to AVDD
Shorted to VSS
Internal (AD sampling capacitor)
C_HOLD shorted to VSS
C_HOLD shorted to AVDD
Otherwise
The bit is ignored
ADIPEN: A/D Inverted Precharge Enable bit
If ADDSEN = 1:
1 = The precharge and guard signals in the second conversion cycle are the opposite polarity of the
first cycle
0 = Both Conversion cycles use the precharge and guards specified by ADPPOL and ADGPOL
Otherwise:
The bit is ignored
ADGPOL: Guard Ring Polarity Selection bit
1 = ADC guard ring outputs start as digital high during precharge stage
0 = ADC guard ring outputs start as digital low during precharge stage
Unimplemented: Read as ‘0’
ADDSEN: Double-Sample Enable bit
1 = See Table 23-5.
0 = One conversion is performed for each trigger
TABLE 23-5: EXAMPLE OF REGISTER VALUES FOR ACCUMULATE AND AVERAGE MODES
Trigger
ADCONT
0
1
Sample
n
ADRES
ADPREV
ADPSIS
0
1
ADACC
T1
T1
1
S(n)
S(n-1)
ADFLTR(n-1)
ADACC(n-1)-S(n-1)
T2
—
2
S(n)
S(n-1)
ADFLTR(n-2)
ADACC(n-1)+S(n-1)
T3
T2
3
S(n)
S(n-1)
ADFLTR(n-1)
ADACC(n-1)-S(n-1)
T4
—
4
S(n)
S(n-1)
ADFLTR(n-2)
ADACC(n-1)+S(n-1)
T5
T3
5
S(n)
S(n-1)
ADFLTR(n-1)
ADACC(n-1)-S(n-1)
T6
—
6
S(n)
S(n-1)
ADFLTR(n-2)
ADACC(n-1)+S(n-1)
DS40001824A-page 358
Preliminary
 2016 Microchip Technology Inc.