PIC16LF18854 Datasheet, PDF(11/668 Page) Microchip Technology – C Compiler Optimized RISC Architecture

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PIC16LF18854 Datasheet, PDF (11/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

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TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16(L)F18876)

RA0 2 17 19 19

RA1 3 18 20 20

RA2 4 19 21 21

RA3 5 20 22 22

RA4 6 21 23 23

RA5 7 22 24 24

ANA0

ANA1

ANA2

ANA3

ANA4

ANA5

â

â

C1IN0- â

C2IN0-

â

â

C1IN1- â

C2IN1-

VREF- DAC1OUT1 C1IN0+ â

C2IN0+

VREF+

â

C1IN1+ â

â

â

â

â

â

â

â

â

â

â

â

â

â

SS1(1)

â

â

â

â

â

â

â

â

â

â MDCARL(1)

â

â MDCARH(1) T0CKI(1)

â

MDSRC(1)

â

â

â

â

â

CCP5(1)

â

â

CLCIN0(1) â

â IOCA0

â

â

CLCIN1(1) â

â IOCA1

â

â

â

â â IOCA2

â

â

â

â â IOCA3

â

â

â

â â IOCA4

â

â

â

â â IOCA5

â

RA6 14 29 33 31 ANA6

â

â

â

â

â

â

RA7 13 28 32 30 ANA7

â

RB0 33 8 9 8

ANB0

â

RB1 34 9 10 9

ANB1

â

RB2 35 10 11 10 ANB2

â

RB3 36 11 12 11 ANB3

â

RB4 37 12 14 14 ANB4

â

ADCACT(1)

RB5 38 13 15 15 ANB5

â

â

â

â

â

â

â

C2IN1+ ZCD SS2(1)

â

â

C1IN3- â SCL2(3,4) â

C2IN3-

SCK2(1)

â

â

â SDA2(3,4) â

SDI2(1)

â

C1IN2- â

â

â

C2IN2-

â

â

â

â

â

â

â

â

â

â

RB6 39 14 16 16 ANB6

â

â

â

â

â

â

RB7 40 15 17 17 ANB7

â DAC1OUT2 â

â

â

â

â

â

â

â

â

â â IOCA6 OSC2

CLKOUT

â

â

â

â

â

â â IOCA7 OSC1

CLKIN

â

â

CCP4(1) CWG1IN(1)

â

â

â INT(1)

â

IOCB0

â

â

â

CWG2IN(1)

â

â â IOCB1

â

â

â

â

CWG3IN(1)

â

â â IOCB2

â

â

â

â

â

T5G(1)

â

SMTWIN2(1)

â

T1G(1)

CCP3(1)

SMTSIG2(1)

â

â

â

â

T6IN(1)

â

â

â

â â IOCB3

â

â

â

â â IOCB4

â

â

â

â â IOCB5

â

â

CLCIN2(1) â

â IOCB6 ICSPCLK

â

CLCIN3(1) â

â IOCB7 ICSPDAT

Note 1:

2:

3:

4:

This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 13-1 for details on which port pins may be

used for this signal.

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 13-3.

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.

These pins are configured for I2C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input

logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I2C specific or SMbus input buffer thresholds.

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