PIC16LF18854 Datasheet, PDF (377/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

FIGURE 24-1:
DIRECT DIGITAL SYNTHESIS MODULE SIMPLIFIED BLOCK DIAGRAM
reserved
reserved
CLC4_out
CLC3_out
CLC2_out
CLC1_out
HFINTOSC
FOSC
111
110
101
100
011
010
001
000
NxCKS<2:0> ₃
NCOxINCU NCOxINCH NCOxINCL
20
(1)
INCBUFU INCBUFH INCBUFL
20
20
NCOx_clk
NCO_overflow
Adder
20
NCOxACCU NCOxACCH NCOxACCL
20
Fixed Duty
Cycle Mode
Circuitry
DQ
NCO_interrupt
DQ
_
Q
EN
Ripple
Counter
R
3
NxPWS<2:0>
SQ
_
RQ
Pulse
Frequency
Mode Circuitry
0
1
NxPFM NxPOL
Rev. 10-000028C
2/2/2015
set bit
NCOxIF
TRIS bit
NCOxOUT
NCOx_out
To Peripherals
DQ
Q1
NxOUT
Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the
second rising edge of the NCOx_clk signal that occurs immediately after a write to NCOxINCL register. The buffers are not user-accessible and are shown here for reference.