PIC16LF18854 Datasheet, PDF (322/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
22.1 CLCx Setup
Programming the CLCx module is performed by
configuring the four stages in the logic signal flow. The
four stages are:
• Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
22.1.1 DATA SELECTION
There are 32 signals available as inputs to the
configurable logic. Four 32-input multiplexers are used
to select the inputs to pass on to the next stage.
Data selection is through four multiplexers as indicated
on the left side of Figure 22-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 22-2 correlates the generic input name to the
actual signal for each CLC module. The column labeled
‘LCxDyS<4:0> Value’ indicates the MUX selection code
for the selected data input. LCxDyS is an abbreviation
for the MUX select input codes: LCxD1S<4:0> through
LCxD4S<4:0>.
Data inputs are selected with CLCxSEL0 through
CLCxSEL3 registers (Register 22-3 through
Register 22-6).
Note: Data selections are undefined at power-up.
TABLE 22-2: CLCx DATA INPUT SELECTION
LCxDyS<4:0>
Value
CLCx Input Source
110000 to 111111 [48+]
101111 [47]
101110 [46]
101101 [45]
101100 [44]
101011 [43]
101010 [42]
101001 [41]
101000 [40]
100111 [39]
100110 [38]
100101 [37]
100100 [36]
100011 [35]
100010 [34]
100001 [33]
100000 [32]
011111 [31]
011110 [30]
011101 [29]
011100 [28]
011011 [27]
011010 [26]
011001 [25]
011000 [24]
010111 [23]
010110 [22]
010101 [21]
010100 [20]
010011 [19]
010010 [18]
010001 [17]
010000 [16]
001111 [15]
001110 [14]
001101 [13]
001100 [12]
001011 [11]
001010 [10]
001001 [9]
001000 [8]
000111 [7]
000110 [6]
000101 [5]
000100 [4]
000011 [3]
000010 [2]
000001 [1]
000000 [0]
Reserved
CWG3B output
CWG3A output
CWG2B output
CWG2A output
CWG1B output
CWG1A output
MSSP2 SCK output
MSSP2 SDO output
MSSP1 SCK output
MSSP1 SDO output
EUSART (TX/CK) output
EUSART (DT) output
CLC4 output
CLC3 output
CLC2 output
CLC1 output
DSM output
IOCIF
ZCD output
Comparator 2 output
Comparator 1 output
NCO1 output
PWM7 output
PWM6 output
CCP5 output
CCP4 output
CCP3 output
CCP2 output
CCP1 output
SMT2 output
SMT1 output
TMR6 to PR6 match
TMR5 overflow
TMR4 to PR4 match
TMR3 overflow
TMR2 to PR2 match
TMR1 overflow
TMR0 overflow
CLKR output
FRC
SOSC
LFINTOSC
HFINTOSC
FOSC
CLCIN3PPS
CLCIN2PPS
CLCIN1PPS
CLCIN0PPS
DS40001824A-page 322
Preliminary
 2016 Microchip Technology Inc.