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PIC16LF18854 Datasheet, PDF (121/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture
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PIC16(L)F18856/76
TABLE 6-1: NOSC/COSC BIT SETTINGS
NOSC<2:0>/
COSC<2:0>
Clock Source
111
EXTOSC(1)
110
HFINTOSC(2)
101
LFINTOSC
100
SOSC
011
Reserved (it operates like
NOSC = 110)
010
EXTOSC with 4x PLL(1)
001
HFINTOSC with 2x PLL(1)
000
Reserved (it operates like
NOSC = 110)
Note 1:
2:
EXTOSC configured by the FEXTOSC bits of
Configuration Word 1 (Register 4-1).
HFINTOSC settings are configured with the
HFFRQ bits of the OSCFRQ register
(Register 6-6).
TABLE 6-2: NDIV/CDIV BIT SETTINGS
NDIV<3:0>/
CDIV<3:0>
Clock divider
1111-1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Reserved
512
256
128
64
32
16
8
4
2
1
REGISTER 6-3: OSCCON3: OSCILLATOR CONTROL REGISTER 3
R/W/HC-0/0 R/W-0/0
U-0
R-0/0
R-0/0
U-0
U-0
U-0
CSWHOLD SOSCPWR
—
ORDY
NOSCR
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
CSWHOLD: Clock Switch Hold bit
1 = Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready
0 = Clock switch may proceed when the oscillator selected by NOSC is ready; if this bit
is clear at the time that NOSCR becomes ‘1’, the switch will occur
SOSCPWR: Secondary Oscillator Power Mode Select bit
1 = Secondary oscillator operating in High-power mode
0 = Secondary oscillator operating in Low-power mode
x = Bit is ignored
Unimplemented: Read as ‘0’.
ORDY: Oscillator Ready bit (read-only)
1 = OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC
0 = A clock switch is in progress
NOSCR: New Oscillator is Ready bit (read-only)
1 = A clock switch is in progress and the oscillator selected by NOSC indicates a “ready” condition
0 = A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready
Unimplemented: Read as ‘0’
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 121
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