PIC16LF18854 Datasheet, PDF (435/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

FIGURE 29-11:
LOW LEVEL RESET, EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 01110)
MODE
0b01110
Rev. 10-000 202B
5/30/201 4
TMRx_clk
PRx
Instruction⁽¹⁾
BS F
5
BS F
ON
TMRx_ers
TMRx
0
12345
0
1
0
12345
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.