PIC16LF18854 Datasheet, PDF (449/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
30.2.1 CCPX PIN CONFIGURATION
The software must configure the CCPx pin as an output
by clearing the associated TRIS bit and defining the
appropriate output pin through the RxyPPS registers.
See Section 13.0 “Peripheral Pin Select (PPS)
Module” for more details.
The CCP output can also be used as an input for other
peripherals.
Note:
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
30.2.2 TIMER1 MODE RESOURCE
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
See Section 28.0 “Timer1/3/5 Module with Gate
Control” for more information on configuring Timer1.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
30.2.3 AUTO-CONVERSION TRIGGER
All CCPx modes set the CCP interrupt flag (CCPxIF).
When this flag is set and a match occurs, an
Auto-conversion Trigger can take place if the CCP
module is selected as the conversion trigger source.
Refer to Section 23.2.6 “Auto-Conversion Trigger”
for more information.
Note:
Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the
Auto-conversion Trigger and the clock
edge that generates the Timer1 Reset, will
preclude the Reset from occurring
30.2.4 COMPARE DURING SLEEP
Since FOSC is shut down during Sleep mode, the
Compare mode will not function properly during Sleep,
unless the timer is running. The device will wake on
interrupt (if enabled).
30.3 PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
Figure 30-3 shows a typical waveform of the PWM
signal.
30.3.1 STANDARD PWM OPERATION
The standard PWM function described in this section is
available and identical for all CCP modules.
The standard PWM mode generates a Pulse-Width
Modulation (PWM) signal on the CCPx pin with up to
ten bits of resolution. The period, duty cycle, and
resolution are controlled by the following registers:
• PR2 registers
• T2CON registers
• CCPRxL registers
• CCPxCON registers
Figure 30-4 shows a simplified block diagram of PWM
operation.
Note:
The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
FIGURE 30-3: CCP PWM OUTPUT SIGNAL
Period
Pulse Width
TMR2 = 0
TMR2 = PR2
TMR2 = CCPRxH:CCPRxL
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 449