PIC16LF18854 Datasheet, PDF (131/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
7.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 8.0
“Power-Saving Operation Modes” for more details.
7.4 INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the PIE0 register. The INTEDG bit
of the INTCON register determines on which edge the
interrupt will occur. When the INTEDG bit is set, the
rising edge will cause the interrupt. When the INTEDG
bit is clear, the falling edge will cause the interrupt. The
INTF bit of the PIR0 register will be set when a valid
edge appears on the INT pin. If the GIE and INTE bits
are also set, the processor will redirect program
execution to the interrupt vector.
7.5 Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these
registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If
modifications to any of these registers are desired, the
corresponding shadow register should be modified and
the value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.
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Preliminary
DS40001824A-page 131