PIC16LF18854 Datasheet, PDF (44/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3-7: PIC16(L)F18856/76 MEMORY MAP BANK 24-31
C00h
C0Bh
C0Ch
BANK 24
Core Registers
(Table 3-2)
C80h
C8Bh
C8Ch
BANK 25
Core Registers
(Table 3-2)
D00h
D0Bh
D0Ch
BANK 26
Core Registers
(Table 3-2)
D80h
D8Bh
D8Ch
BANK 27
Core Registers
(Table 3-2)
E00h
E0Bh
E0Ch
BANK 28
Core Registers
(Table 3-2)
E80h
E8Bh
E8Ch
BANK 29
Core Registers
(Table 3-2)
F00h
F0Bh
F0Ch
BANK 30
Core Registers
(Table 3-2)
F80h
F8Bh
F8Ch
BANK 31
Core Registers
(Table 3-2)
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
C6Fh
CEFh
C70h
CF0h
C7Fh
C20h
C6Fh
General
Purpose
Register
80 Bytes
Common RAM
Accesses
70h – 7Fh
CFFh
CA0h
CBFh
General
Purpose
Register
80 Bytes
Common RAM
Accesses
70h – 7Fh
D6Fh
D70h
D7Fh
Common RAM
Accesses
70h – 7Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
DEFh
DF0h
DFFh
Unimplemented
Read as ‘0’
Common RAM
Accesses
70h – 7Fh
See Table 3-8 for
register mapping
details
See Table 3-9 for
register mapping
details
E6Fh
E70h
E7Fh
Common RAM
Accesses
70h – 7Fh
EEFh
EF0h
EFFh
Common RAM
Accesses
70h – 7Fh
F6Fh
F70h
F7Fh
See Table 3-10
for register
mapping details
Common RAM
Accesses
70h – 7Fh
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
FF0h
FFFh
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
TOSH
Common RAM
Accesses
70h – 7Fh