PIC16LF18854 Datasheet, PDF (296/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
20.3 Selectable Input Sources
The CWG generates the output waveforms from the
input sources in Table 20-2.
TABLE 20-2: SELECTABLE INPUT
SOURCES
Source Peripheral
Signal Name
CWG input PPS pin
CCP1
CCP2
CCP3
CCP4
CCP5
PWM6
PWM7
NCO
Comparator C1
Comparator C2
DSM
CLC1
CLC2
CLC3
CLC4
CWGxIN PPS
CCP1_out
CCP2_out
CCP3_out
CCP4_out
CCP5_out
PWM6_out
PWM7_out
NCO_out
C1OUT_sync
C2OUT_sync
DSM_out
LC1_out
LC2_out
LC3_out
LC4_out
The input sources are selected using the CWGxISM
register.
20.4 Output Control
20.4.1 OUTPUT ENABLES
Each CWG output pin has individual output enable con-
trol. Output enables are selected with the Gx1OEx
<3:0> bits. When an output enable control is cleared,
the module asserts no control over the pin. When an
output enable is set, the override value or active PWM
waveform is applied to the pin per the port priority
selection. The output pin enables are dependent on the
module enable bit, EN of the CWGxCON0 register.
When EN is cleared, CWG output enables and CWG
drive levels have no effect.
20.4.2 POLARITY CONTROL
The polarity of each CWG output can be selected inde-
pendently. When the output polarity bit is set, the corre-
sponding output is active-high. Clearing the output
polarity bit configures the corresponding output as
active-low. However, polarity does not affect the over-
ride levels. Output polarity is selected with the POLx
bits of the CWGxCON1. Auto-shutdown and steering
options are unaffected by polarity.
DS40001824A-page 296
Preliminary
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