PIC16LF18854 Datasheet, PDF (137/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-6: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4
U-0
—
bit 7
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
TMR6IE
TMR5IE
TMR4IE
TMR3IE
R/W-0/0
TMR2IE
R/W-0/0
TMR1IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR6IE: TMR6 to PR6 Match Interrupt Enable bit
1 = Enables the Timer6 to PR6 match interrupt
0 = Disables the Timer6 to PR6 match interrupt
TMR5IE: Timer5 Overflow Interrupt Enable bit
1 = Enables the Timer5 overflow interrupt
0 = Disables the Timer5 overflow interrupt
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enables the Timer4 to PR4 match interrupt
0 = Disables the Timer4 to PR4 match interrupt
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enables the Timer3 overflow interrupt
0 = Enables the Timer3 overflow interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Enables the Timer1 overflow interrupt
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt
controlled by registers PIE1-PIE8.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 137