PIC16LF18854 Datasheet, PDF (147/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-16: PIR5: PERIPHERAL INTERRUPT REQUEST REGISTER 5
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
U-0
R/W/HS-0/0 R/W/HS-0/0
CLC4IF
CLC3IF
CLC2IF
CLC1IF
—
TMR5GIF TMR3GIF
bit 7
R/W/HS-0/0
TMR1GIF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
CLC4IF: CLC4 Interrupt Flag bit
1 = A CLC4OUT interrupt condition has occurred (must be cleared in software)
0 = No CLC4 interrupt event has occurred
bit 6
CLC3IF: CLC3 Interrupt Flag bit
1 = A CLC4OUT interrupt condition has occurred (must be cleared in software)
0 = No CLC4 interrupt event has occurred
bit 5
CLC2IF: CLC2 Interrupt Flag bit
1 = A CLC4OUT interrupt condition has occurred (must be cleared in software)
0 = No CLC4 interrupt event has occurred
bit 4
CLC1IF: CLC1 Interrupt Flag bit
1 = A CLC4OUT interrupt condition has occurred (must be cleared in software)
0 = No CLC4 interrupt event has occurred
bit 3
Unimplemented: Read as ‘0’
bit 2
TMR5GIF: Timer5 Gate Interrupt Flag bit
1 = The Timer5 Gate has gone inactive (the gate is closed)
0 = The Timer5 Gate has not gone inactive
bit 1
TMR3GIF: Timer3 Gate Interrupt Flag bit
1 = The Timer5 Gate has gone inactive (the gate is closed)
0 = The Timer5 Gate has not gone inactive
bit 0
TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = The Timer1 Gate has gone inactive (the gate is closed)
0 = The Timer1 Gate has not gone inactive
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 147