PIC16LF18854 Datasheet, PDF (422/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 28-4: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
PIE1
T1CON
T1GCON
GIE
OSFIF
OSFIE
—
GE
PEIE
CSWIF
CSWIE
—
GPOL
―
―
―
―
―
―
CKPS<5:4>
GTM
GSPM
―
―
―
—
GGO/
DONE
―
―
―
SYNC
GVAL
―
ADTIF
ADTIE
RD16
—
INTEDG
ADIF
ADIE
ON
—
T1GATE
—
—
—
GSS<4:0>
T1CLK
—
—
—
—
CS<3:0>
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
T1CKIPPS
―
―
―
T1CKIPPS<4:0>
T1GPPS
―
―
―
T1GPPS<4:0>
T3CON
—
—
CKPS<5:4>
—
SYNC
RD16
ON
T3GCON
GE
GPOL
GTM
GSPM
GGO/
GVAL
—
—
DONE
T3GATE
—
—
—
GSS<4:0>
T3CLK
—
—
—
—
CS<3:0>
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
T3CKIPPS
―
―
―
T3CKIPPS<4:0>
T3GPPS
―
―
―
T3GPPS<4:0>
T5CON
—
—
CKPS<5:4>
—
SYNC
RD16
ON
T5GCON
GE
GPOL
GTM
GSPM
GGO/
GVAL
—
—
DONE
T5GATE
—
—
—
GSS<4:0>
T5CLK
—
—
—
—
CS<3:0>
TMR5L
Holding Register for the Least Significant Byte of the 16-bit TMR5 Register
TMR5H
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
T5CKIPPS
―
―
―
T5CKIPPS<4:0>
T5GPPS
―
―
―
T5GPPS<4:0>
T0CON0
T0EN
―
T0OUT T016BIT
T0OUTPS<3:0>
CMxCON0
CxON
CxOUT
―
CxPOL
―
CxSP
CxHYS CxSYNC
CCPTMRS0
C4TSEL<1:0>
C3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
CCPTMRS1
—
—
P7TSEL<1:0>
P6TSEL<1:0>
C5TSEL<1:0>
CCPxCON CCPxEN
―
CCPxOUT CCPxFMT
CCPxMODE<3:0>
CLCxSELy
―
―
―
LCxDyS<4:0>
ADACT
―
―
―
ADACT<4:0>
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used with the Timer1 modules.
* Page with register information.
Register
on Page
132
132
134
418
419
421
420
410*
410*
247
247
418
419
421
420
410*
410*
247
247
418
419
421
420
410*
410*
247
247
407
279
456
456
453
329
359
DS40001824A-page 422
Preliminary
 2016 Microchip Technology Inc.