PIC16LF18854 Datasheet, PDF (13/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3: 40/44-PIN ALLOCATION TABLE (PIC16(L)F18876) (CONTINUED)
RE3 1 16 18 18
—
—
—
—
—
—
—
—
—
—
—
—
— — IOCE3 MCLR
VPP
VDD 11, 7, 8, 7,
—
—
—
—
—
—
—
—
—
—
—
—
——
—
—
32 26 28 28
VSS 12, 6, 6, 6,
—
—
31 27 31, 29
30
OUT⁽²⁾ — — — — ADGRDA
—
ADGRDB
—
—
—
—
—
—
—
C1OUT —
SDO1
TX/
DSM
C2OUT
SCK1
CK⁽³⁾
SDO2 DT⁽³⁾
SCK2
—
—
—
—
——
—
—
TMR0
CCP1
CWG1A CLC1OUT NCO CLKR —
—
CCP2
CWG1B CLC2OUT
CCP3
CWG1C CLC3OUT
CCP4
CWG1D CLC4OUT
CCP5
CWG2A
PWM6OUT CWG2B
PWM7OUT CWG2C
CWG2D
CWG3A
CWG3B
CWG3C
CWG3D
Note 1:
2:
3:
4:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to Table 13-1 for details on which port pins may be
used for this signal.
All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in Table 13-3.
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I²C logic levels.; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input
logic levels will be standard TTL/ST, as selected by the INLVL register, instead of the I²C specific or SMbus input buffer thresholds.