PIC16LF18854 Datasheet, PDF(5/668 Page) Microchip Technology – C Compiler Optimized RISC Architecture

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PIC16LF18854 Datasheet, PDF (5/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

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PIC16(L)F18856/76

28-pin QFN (6x6), UQFN (4x4)

RA2 1

RA3 2

RA4 3

RA5 4

VSS 5

RA7 6

RA6 7

PIC16(L)F18856

21 RB3

20 RB2

19 RB1

18 RB0

17 VDD

16 VSS

15 RC7

Note 1:

2:

3:

See Table 2 for location of all peripheral functions.

All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to

float may result in degraded electrical performance or non-functionality.

The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.

40-pin PDIP

VPP/MCLR/RE3 1

RA0 2

RA1 3

RA2 4

RA3 5

RA4 6

RA5 7

RE0 8

RE1 9

RE2 10

VDD 11

VSS 12

RA7 13

RA6 14

RC0 15

RC1 16

RC2 17

RC3 18

RD0 19

RD1 20

40 RB7/ICSPDAT

39 RB6/ICSPCLK

38 RB5

37 RB4

36 RB3

35 RB2

34 RB1

33 RB0

32 VDD

31 VSS

30 RD7

29 RD6

28 RD5

27 RD4

26 RC7

25 RC6

24 RC5

23 RC4

22 RD3

21 RD2

Note 1: See Table 3 for location of all peripheral function.

2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to

float may result in degraded electrical performance or non-functionality.

ï£ 2016 Microchip Technology Inc.

Preliminary

DS40001824A-page 5

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