PIC16LF18854 Datasheet, PDF (413/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

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28.6.2 TIMER GATE SOURCE SELECTION
One of the several different external or internal signal
sources may be chosen to gate the timer and allow the
timer to increment. The gate input signal source can be
selected based on the T1GATE register setting. See the
T1GATE register (Register 28-4) description for a
complete list of the available gate sources. The polarity
for each available source is also selectable. Polarity
selection is controlled by the GPOL bit of the T1GCON
register.
28.6.2.1 T1G Pin Gate Operation
The T1G pin is one source for the timer gate control. It
can be used to supply an external source to the time
gate circuitry.
28.6.2.2 Timer0 Overflow Gate Operation
When Timer0 overflows, or a period register match
condition occurs (in 8-bit mode), a low-to-high pulse will
automatically be generated and internally supplied to
the Timer1 gate circuitry.
28.6.2.3 Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can
be selected as a source for the timer gate control. The
Comparator 1 output can be synchronized to the timer
clock or left asynchronous. For more information see
Section 18.4.1
“Comparator
Output
Synchronization”.
28.6.2.4 Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation
can be selected as a source for the timer gate control.
The Comparator 2 output can be synchronized to the
timer clock or left asynchronous. For more information
see Section 18.4.1 “Comparator Output
Synchronization”.
28.6.3 TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a timer gate sig-
nal, as opposed to the duration of a single level pulse.
The timer gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 28-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
GTM bit of the T1GCON register. When the GTM bit is
cleared, the flip-flop is cleared and held clear. This is
necessary in order to control which edge is measured.
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
28.6.4
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
GSPM bit in the T1GCON register. Next, the
GGO/DONE bit in the T1GCON register must be set.
The timer will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the
GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment the timer until
the GGO/DONE bit is once again set in software. See
Figure 28-5 for timing details.
If the Single-Pulse Gate mode is disabled by clearing the
GSPM bit in the T1GCON register, the GGO/DONE bit
should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the timer gate
source to be measured. See Figure 28-6 for timing
details.
28.6.5 TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the GVAL bit in the T1GCON reg-
ister. The GVAL bit is valid even when the timer gate is
not enabled (GE bit is cleared).
28.6.6 TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of T1GVAL
occurs, the TMR1GIF flag bit in the PIR5 register will be
set. If the TMR1GIE bit in the PIE5 register is set, then
an interrupt will be recognized.
The TMR1GIF flag bit operates even when the timer
gate is not enabled (TMR1GE bit is cleared).
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Preliminary
DS40001824A-page 413