PIC16LF18854 Datasheet, PDF (145/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-14: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
U-0
U-0
R-0
R-0
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
—
—
RCIF
TXIF
BCL2IF
SSP2IF
BCL1IF
bit 7
R/W/HS-0/0
SSP1IF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware clearable
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
RCIF: EUSART Receive Interrupt Flag (read-only) bit ⁽¹⁾
1 = The EUSART receive buffer is not empty (contains at least one byte)
0 = The EUSART receive buffer is empty
TXIF: EUSART Transmit Interrupt Flag (read-only) bit⁽²⁾
1 = The EUSART transmit buffer contains at least one unoccupied space
0 = The EUSART transmit buffer is currently full. The application firmware should not write to TXREG
again, until more room becomes available in the transmit buffer.
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1 = A bus collision was detected (must be cleared in software)
0 = No bus collision was detected
SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting for the Transmission/Reception/Bus Condition in progress
BCL1IF: MSSP1 Bus Collision Interrupt Flag bit
1 = A bus collision was detected (must be cleared in software)
0 = No bus collision was detected
SSP1IF: Synchronous Serial Port (MSSP1) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting for the Transmission/Reception/Bus Condition in progress
Note 1:
2:
The RCIF flag is a read-only bit. To clear the RCIF flag, the firmware must read from RCREG enough
times to remove all bytes from the receive buffer.
The TXIF flag is a read-only bit, indicating if there is room in the transmit buffer. To clear the TXIF flag, the
firmware must write enough data to TXREG to completely fill all available bytes in the buffer. The TXIF flag
does not indicate transmit completion (use TRMT for this purpose instead).
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 145