PIC16LF18854 Datasheet, PDF (40/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3-3: PIC16(L)F18856 MEMORY MAP BANK 0-7
000h
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
BANK 0
Core Registers
(Table 3-2)
PORTA
PORTB
PORTC
—
PORTE
TRISA
TRISB
TRISC
—
—
LATA
LATB
LATC
—
—
—
TMR0L
TMR0H
T0CON0
T0CON1
080h
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
BANK 1
Core Registers
(Table 3-2)
ADRESL
ADRESH
ADPREVL
ADPREVH
ADACCL
ADACCH
—
ADCON0
ADCON1
ADCON2
ADCON3
ADSTAT
ADCLK
ADACT
ADREF
ADCAP
ADPRE
ADACQ
ADPCH
—
100h
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
BANK 2
Core Registers
(Table 3-2)
ADCNT
ADRPT
ADLTHL
ADLTHH
ADUTHL
ADUTHH
ADSTPTL
ADSTPTH
ADFLTRL
ADFLTRH
ADERRL
ADERRH
—
RC1REG
TX1REG
SP1BRGL
SP1BRGH
RC1STA
TX1STA
BAUD1CON
180h
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
BANK 3
Core Registers
(Table 3-2)
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
—
—
—
SSP2BUF
SSP2ADD
SSP2MSK
SSP2STAT
SSP2CON1
SSP2CON2
SSP2CON3
—
—
—
200h
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
BANK 4
Core Registers
(Table 3-2)
TMR1L
TMR1H
T1CON
T1GCON
T1GATE
T1CLK
TMR3L
TMR3H
T3CON
T3GCON
T3GATE
T3CLK
TMR5L
TMR5H
T5CON
T5GCON
T5GATE
T5CLK
CCPTMRS0
CCPTMRS1
280h
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
BANK 5
Core Registers
(Table 3-2)
T2TMR
T2PR
T2CON
T2HLT
T2CLKCON
T2RST
T4TMR
T4PR
T4CON
T4HLT
T4CLKCON
T4RST
T6TMR
T6PR
T6CON
T6HLT
T6CLKCON
T6RST
—
—
300h
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
BANK 6
Core Registers
(Table 3-2)
CCPR1L
CCPR1H
CCP1CON
CCP1CAP
CCPR2L
CCPR2H
CCP2CON
CCP2CAP
CCPR3L
CCPR3H
CCP3CON
CCP3CAP
CCPR4L
CCPR4H
CCP4CON
CCP4CAP
CCPR5L
CCPR5H
CCP5CON
CCP5CAP
380h
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
BANK 7
Core Registers
(Table 3-2)
PWM6DCL
PWM6DCH
PWM6CON
—
PWM7DCL
PWM7DCH
PWM7CON
—
—
—
—
—
—
—
—
—
—
—
—
—
General
Purpose
Register
96 Bytes
07Fh
Legend:
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
0EFh
0F0h
0FFh
Common RAM
(Accesses
70h – 7Fh)
16Fh
170h
17Fh
Common RAM
(Accesses
70h – 7Fh)
1EFh
1F0h
1FFh
Common RAM
(Accesses
70h – 7Fh)
26Fh
270h
27Fh
Common RAM
(Accesses
70h – 7Fh)
2EFh
2F0h
2FFh
Common RAM
(Accesses
70h – 7Fh)
36Fh
370h
37Fh
Common RAM
(Accesses
70h – 7Fh)
3EFh
3F0h
3FFh
Common RAM
(Accesses
70h – 7Fh)
= Unimplemented data memory locations, read as ‘0’.