PIC16LF18854 Datasheet, PDF (421/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 28-4: TxGATE TIMER1/3/5 GATE SELECT REGISTER
U-0
U-0
U-0
R/W-0/u
R/W-0/u
R/W-0/u
—
—
—
GSS<4:0>
bit 7
R/W-0/u
R/W-0/u
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
GSS<4:0>: Timer1 Gate Select bits
11111 = Reserved
•
•
•
11001 = Reserved
11000 = LC4_out
10111 = LC3_out
10110 = LC2_out
10101 = LC1_out
10100 = ZCD1_output
10011 = C2OUT_sync
10010 = C1OUT_sync
10001 = DDS_out
10000 = PWM7_out
01111 = PWM6_out
01110 = CCP5_out
01101 = CCP4_out
01100 = CCP3_out
01011 = CCP2_out
01010 = CCP1_out
01001 = SMT2_match
01000 = SMT1_match
00111 = TMR6_postscaled
00110 = TMR5 overflow output⁽³⁾
00101 = TMR4_postscaled
00100 = TMR3 overflow output⁽²⁾
00011 = TMR2_postscaled
00010 = TMR1 overflow output⁽¹⁾t
00001 = TMR0 overflow output
00000 = T1GPPS
Note 1:
2:
3:
For Timer1, this bit is Reserved.
For Timer3, this bit is Reserved.
For Timer5, this bit is Reserved.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 421