PIC16LF18854 Datasheet, PDF (241/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
13.0 PERIPHERAL PIN SELECT
(PPS) MODULE
The Peripheral Pin Select (PPS) module connects
peripheral inputs and outputs to the device I/O pins.
Only digital signals are included in the selections. All
analog inputs and outputs remain fixed to their
assigned pins. Input and output selections are
independent as shown in the simplified block diagram
Figure 13-1.
TABLE 13-1: PPS INPUT SIGNAL ROUTING OPTIONS
Input Signal Input Register
Name
Name
INT
T0CKI
T1CKI
T1G
T3CKI
T3G
T5CKI
T5G
T2IN
T4IN
T6IN
CCP1
CCP2
CCP3
CCP4
CCP5
SMTWIN1
SMTSIG1
SMTWIN2
SMTSIG2
CWG1IN
CWG2IN
CWG3IN
MDCARL
MDCARH
MDMSRC
CLCIN0
CLCIN1
CLCIN2
INTPPS
T0CKIPPS
T1CKIPPS
T1GPPS
T3CKIPPS
T3GPPS
T5CKIPPS
T5GPPS
T2INPPS
T4INPPS
T6INPPS
CCP1PPS
CCP2PPS
CCP3PPS
CCP4PPS
CCP5PPS
SMTWIN1PPS
SMTSIG1PPS
SMTWIN2PPS
SMTSIG2PPS
CWG1PPS
CWG2PPS
CWG3PPS
MDCARLPPS
MDCARHPPS
MDSRCPPS
CLCIN0PPS
CLCIN1PPS
CLCIN2PPS
Default
Location
at POR
RB0
RA4
RC0
RB5
RC0
RC0
RC2
RB4
RC3
RC5
RB7
RC2
RC1
RB5
RB0
RA4
RC0
RC1
RB4
RB5
RB0
RB1
RB2
RA3
RA4
RA5
RA0
RA1
RB6
Remappable to Pins of PORTx
PIC16F18856
PIC16F18876
PORTA
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PORTB
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PORTC
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PORTA
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PORTB
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PORTC
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PORTD
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PORTE
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 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 241