PIC16LF18854 Datasheet, PDF (460/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
The I²C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 31-2 is a block diagram of the I²C interface
module in Master mode. Figure 31-3 is a diagram of the
I²C interface module in Slave mode.
Note 1: In devices with more than one MSSP
module, it is very important to pay close
attention to SSPxCONx register names.
SSPxCON1 and SSPxCON2 registers
control different operational aspects of
the same module, while SSPxCON1 and
SSP2CON1 control the same features for
two different modules.
2: Throughout this section, generic refer-
ences to an MSSPx module in any of its
operating modes may be interpreted as
being equally applicable to MSSPx or
MSSP2. Register names, module I/O sig-
nals, and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module
when required.
FIGURE 31-2:
MSSP BLOCK DIAGRAM (I²C MASTER MODE)
Internal
data bus
SSPDATPPS⁽¹⁾
Read
Write
SDA
PPS
SDA in
SSPxBUF
RxyPPS⁽¹⁾
PPS
SSPSR
MSb
Shift
Clock
LSb
[SSPM<3:0>]
Baud Rate
Generator
(SSPxADD)
SSPCLKPPS⁽²⁾
SCL
PPS
Start bit, Stop bit,
Acknowledge
Generate (SSPxCON2)
PPS
RxyPPS⁽²⁾
SCL in
Bus Collision
Start bit detect,
Stop bit detect
Write collision detect
Clock arbitration
State counter for
end of XMIT/RCV
Address Match detect
Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPxCON2)
Set SSPxIF, BCL1IF
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
DS40001824A-page 460
Preliminary
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