PIC16LF18854 Datasheet, PDF (30/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 1-3: PIC16F18876 PINOUT DESCRIPTION (CONTINUED)
Name
RC6/ANC6/CK⁽³⁾/IOCC6
Function
RC6
Input Type
TTL/ST
Output Type
Description
CMOS/OD General purpose I/O.
ANC6
CK⁽³⁾
AN
TTL/ST
—
CMOS/OD
ADC Channel C6 input.
EUSART synchronous mode clock input/output.
RC7/ANC7/RX⁽¹⁾/DT⁽³⁾/IOCC7
IOCC6
RC7
TTL/ST
TTL/ST
—
CMOS/OD
Interrupt-on-change input.
General purpose I/O.
ANC7
RX⁽¹⁾
DT⁽³⁾
AN
TTL/ST
TTL/ST
—
—
CMOS/OD
ADC Channel C7 input.
EUSART Asynchronous mode receiver data input.
EUSART Synchronous mode data input/output.
IOCC7
TTL/ST
—
Interrupt-on-change input.
RD0
RD0
TTL/ST
CMOS/OD General purpose I/O.
AND0
AN
—
ADC Channel D0 input.
RD1
RD1
TTL/ST
CMOS/OD General purpose I/O.
AND1
AN
—
ADC Channel D1 input.
RD2
RD2
TTL/ST
CMOS/OD General purpose I/O.
AND2
AN
—
ADC Channel D2 input.
RD3
RD3
TTL/ST
CMOS/OD General purpose I/O.
AND3
AN
—
ADC Channel D3 input.
RD4
RD4
TTL/ST
CMOS/OD General purpose I/O.
AND4
AN
—
ADC Channel D4 input.
RD5
RD5
TTL/ST
CMOS/OD General purpose I/O.
AND5
AN
—
ADC Channel D5 input.
RD6
RD6
TTL/ST
CMOS/OD General purpose I/O.
AND6
AN
—
ADC Channel D6 input.
RD7
RD7
TTL/ST
CMOS/OD General purpose I/O.
AND7
AN
—
ADC Channel D7 input.
RE0
RE0
TTL/ST
CMOS/OD General purpose I/O.
ANE0
AN
—
ADC Channel E0 input.
RE1
RE1
TTL/ST
CMOS/OD General purpose I/O.
ANE1
AN
—
ADC Channel E1 input.
RE2
RE2
TTL/ST
CMOS/OD General purpose I/O.
ANE2
AN
—
ADC Channel E2 input.
RE3/IOCE3/MCLR/VPP
RE3
IOCE3
TTL/ST
TTL/ST
—
General purpose input-only (when MCLR is disabled by
config bit).
—
Interrupt-on-change input.
MCLR
ST
—
Master clear input with internal weak pull-up resistor.
VPP
HV
—
ICSP™ high voltage programming mode entry input.
VDD
VDD
Power
—
Positive supply voltage input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output
OD = Open-Drain
TTL = TTL compatible input
ST
= Schmitt Trigger input with CMOS levels
I²C = Schmitt Trigger input with I²CHV=
High Voltage XTAL= Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I²C specific or SMBus input buffer thresholds.
DS40001824A-page 30
Preliminary
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