PIC16LF18854 Datasheet, PDF (6/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
40-pin UQFN (5x5)
RC7 1
RD4 2
RD5 3
RD6 4
RD7 5
VSS 6
VDD 7
RB0 8
RB1 9
RB2 10
PIC16(L)F18876
30 RC0
29 RA6
28 RA7
27 _VSS
26 VDD
25 RE2
24 RE1
23 RE0
22 RA5
21 RA4
Note 1:
2:
3:
See Table 3 for location of all peripheral functions.
All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.
44-pin TQFP (10x10)
RC7
1
RD4
2
RD5
3
RD6
4
RD7
5
VSS
6
VDD
7
RB0
8
RB1
9
RB2
10
RB3
11
PIC16(L)F18876
33
NC
32
RC0
31
RA6
30
RA7
29
VSS
28
VDD
27
RE2
26
RE1
25
RE0
24
RA5
23
RA4
Note 1: See Table 3 for location of all peripheral functions.
2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to
float may result in degraded electrical performance or non-functionality.
DS40001824A-page 6
Preliminary
 2016 Microchip Technology Inc.