PIC16LF18854 Datasheet, PDF (23/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
Name
RC4/ANC4/SDA1^(3,4)/SDI1⁽¹⁾/IOCC4
Function
RC4
Input
Type
TTL/ST
Output Type
CMOS/OD
General purpose I/O.
Description
ANC4
SDA1^(3,4)
SDI1⁽¹⁾
AN
I²C/
SMBus
TTL/ST
—
ADC Channel C4 input.
OD
MSSP1 I²C serial data input/output.
—
MSSP1 SPI serial data input.
RC5/ANC5/T4IN⁽¹⁾/IOCC5
IOCC4
RC5
TTL/ST
TTL/ST
—
CMOS/OD
Interrupt-on-change input.
General purpose I/O.
ANC5
T4IN⁽¹⁾
AN
TTL/ST
—
ADC Channel C5 input.
—
Timer4 external input.
RC6/ANC6/CK⁽³⁾/IOCC6
IOCC5
RC6
TTL/ST
TTL/ST
—
CMOS/OD
Interrupt-on-change input.
General purpose I/O.
ANC6
CK⁽³⁾
AN
TTL/ST
—
CMOS/OD
ADC Channel C6 input.
EUSART synchronous mode clock input/output.
RC7/ANC7/RX⁽¹⁾/DT⁽³⁾/IOCC7
IOCC6
RC7
TTL/ST
TTL/ST
—
CMOS/OD
Interrupt-on-change input.
General purpose I/O.
ANC7
RX⁽¹⁾
DT⁽³⁾
AN
TTL/ST
TTL/ST
—
—
CMOS/OD
ADC Channel C7 input.
EUSART Asynchronous mode receiver data input.
EUSART Synchronous mode data input/output.
IOCC7
TTL/ST
—
Interrupt-on-change input.
RE3/IOCE3/MCLR/VPP
RE3
IOCE3
TTL/ST
TTL/ST
—
General purpose input only (when MCLR is disabled by the
Configuration bit).
—
Interrupt-on-change input.
MCLR
ST
—
Master clear input with internal weak pull up resistor.
VPP
HV
—
ICSP™ High-Voltage Programming mode entry input.
VDD
VDD
Power
—
Positive supply voltage input.
Legend: AN = Analog input or output
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
OD = Open-Drain
I²C = Schmitt Trigger input with I²C
HV = High Voltage
XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I²C specific or SMBus input buffer thresholds.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 23