PIC16LF18854 Datasheet, PDF (150/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-19: PIR7: PERIPHERAL INTERRUPT REQUEST REGISTER 7
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
U-0
R/W/HS-0/0 R/W/HS-0/0
SCANIF
CRCIF
NVMIF
NCO1IF
—
bit 7
CWG3IF
CWG2IF
R/W/HS-0/0
CWG1IF
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7
SCANIF: Program Memory Scanner Interrupt Flag bit
1 = The operation has completed (a SCANGO 1 to 0 transition has occurred)
0 = No operation is pending or the operation is still in progress
bit 6
CRCIF: CRC Interrupt Flag bit
1 = The operation has completed (a BUSY 1 to 0 transition has occurred)
0 = No operation is pending or the operation is still in progress
bit 5
NVMIF: Non-Volatile Memory (NVM) Interrupt Flag bit
1 = The requested NVM operation has completed
0 = NVM interrupt not asserted
bit 4
NCO1IF: Numerically Controlled Oscillator (NCO) Interrupt Flag bit
1 = The NCO has rolled over
0 = No CLC4 interrupt event has occurred
bit 3
Unimplemented: Read as ‘0’
bit 2
CWG3IF: CWG3 Interrupt Flag bit
1 = CWG3 has gone into shutdown
0 = CWG3 is operating normally, or interrupt cleared
bit 1
CWG2IF: CWG2 Interrupt Flag bit
1 = CWG2 has gone into shutdown
0 = CWG3 is operating normally, or interrupt cleared
bit 0
CWG1IF: CWG1 Interrupt Flag bit
1 = CWG1 has gone into shutdown
0 = CWG1 is operating normally, or interrupt cleared
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
DS40001824A-page 150
Preliminary
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