PIC16LF18854 Datasheet, PDF (300/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
20.8 Dead-Band Uncertainty
When the rising and falling edges of the input source
are asynchronous to the CWG clock, it creates uncer-
tainty in the dead-band time delay. The maximum
uncertainty is equal to one CWG clock period. Refer to
Equation 20-1 for more details.
EQUATION 20-1: DEAD-BAND
UNCERTAINTY
TDEADBAND_UNCERTAINTY = _{F----c---w----g---1_---c---l-o---c---k-}
Example:
FCWG_CLOCK = 16 MHz
Therefore:
TDEADBAND_UNCERTAINTY = --------------1--------------
Fcwg_clock
= --------1----------
16 M H z
= 62.5ns
FIGURE 20-8:
MODE0
CWGxA
CWGxB
CWGxC
CWGxD
CWGx_data
EXAMPLE OF PWM DIRECTION CHANGE
No delay
CWGxDBR
No delay
CWGxDBF
Note 1:WGPOL{ABCD} = 0
2: The direction bit MODE<0> (Register 20-1) can be written any time during the PWM cycle, and takes effect at the
next rising CWGx_data.
3: When changing directions, CWGxA and CWGxC switch at rising CWGx_data; modulated CWGxB and CWGxD are
held inactive for the dead band duration shown; dead band affects only the first pulse after the direction change.
FIGURE 20-9:
CWGx_clock
CWG HALF-BRIDGE MODE OPERATION
CWGxA
CWGxC
CWGxB
CWGxD
Rising Event Dead Band
Rising Event D
Falling Event Dead Band
Falling Event Dead Band
CWGx_data
Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out
DS40001824A-page 300
Preliminary
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