PIC16LF18854 Datasheet, PDF (55/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

TABLE 3-13: SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-31 (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 4
CPU CORE REGISTERS; see Table 3-2 for specifics
20Ch
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
20Dh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
20Eh
T1CON
—
—
CKPS<1:0>
—
SYNC
RD16
ON
20Fh
T1GCON
GE
GPOL
GTM
GSPM
GGO/DONE
GVAL
—
—
210h
T1GATE
—
—
—
GSS<4:0>
211h
T1CLK
—
—
—
—
CS<3:0>
212h
TMR3L
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
213h
TMR3H
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
214h
T3CON
—
—
CKPS<1:0>
—
SYNC
RD16
ON
215h
T3GCON
GE
GPOL
GTM
GSPM
GGO/DONE
GVAL
—
—
216h
T3GATE
—
—
—
GSS<4:0>
217h
T3CLK
—
—
—
—
CS<3:0>
218h
TMR5L
Holding Register for the Least Significant Byte of the 16-bit TMR5 Register
219h
TMR5H
Holding Register for the Most Significant Byte of the 16-bit TMR5 Register
21Ah
T5CON
—
—
CKPS<1:0>
—
SYNC
RD16
ON
21Bh
T5GCON
GE
GPOL
GTM
GSPM
GGO/DONE
GVAL
—
—
21Ch
T5GATE
—
—
—
GSS<4:0>
21Dh
T5CLK
—
—
—
—
CS<3:0>
21Eh
CCPTMRS0
C4TSEL<1:0>
C3TSEL<1:0>
C2TSEL<1:0>
C1TSEL<1:0>
21Fh
CCPTMRS1
—
—
P7TSEL<1:0>
P6TSEL<1:0>
C5TSEL<1:0>
Legend:
Note 1:
2:
x = unknown, u = unchanged, q =depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations unimplemented, read as ‘0’.
Register present on PIC16F18855/75 devices only.
Unimplemented, read as ‘1’.
Value on:
POR, BOR
Value on all
other Resets
0000 0000
0000 0000
--00 -000
0000 0x--
---0 0000
---- 0000
0000 0000
0000 0000
--00 -000
0000 0x--
---0 0000
---- 0000
0000 0000
0000 0000
--00 -000
0000 0x--
---0 0000
---- 0000
0101 0101
--01 0101
uuuu uuuu
uuuu uuuu
--uu -uuu
uuuu ux--
---u uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
--uu -uuu
uuuu ux--
---u uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
--uu -uuu
uuuu ux--
---u uuuu
---- uuuu
0101 0101
--01 0101