PIC16LF18854 Datasheet, PDF (543/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
32.7 Interrupts
The SMT can trigger an interrupt under three different
conditions:
• PW Acquisition Complete
• PR Acquisition Complete
• Counter Period Match
The interrupts are controlled by the PIR and PIE
registers of the device.
32.7.1
PW AND PR ACQUISITION
INTERRUPTS
The SMT can trigger interrupts whenever it updates the
SMTxCPW and SMTxCPR registers, the circum-
stances for which are dependent on the SMT mode,
and are discussed in each mode’s specific section. The
SMTxCPW interrupt is controlled by SMTxPWAIF and
SMTxPWAIE bits in registers PIR8 and PIE8, respec-
tively. The SMTxCPR interrupt is controlled by the
SMTxPRAIF and SMTxPRAIE bits, also located in reg-
isters PIR8 and PIE8, respectively.
In synchronous SMT modes, the interrupt trigger is
synchronized to the SMTxCLK. In Asynchronous
modes, the interrupt trigger is asynchronous. In either
mode, once triggered, the interrupt will be synchro-
nized to the CPU clock.
32.7.2
COUNTER PERIOD MATCH
INTERRUPT
As described in Section 32.1.2 “Period Match
interrupt”, the SMT will also interrupt upon SMTxTMR,
matching SMTxPR with its period match limit functionality
described in Section 32.3 “Halt Operation”. The period
match interrupt is controlled by SMTxIF and SMTxIE,
located in registers PIR8 and PIE8, respectively.
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Preliminary
DS40001824A-page 543