PIC16LF18854 Datasheet, PDF (295/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
20.1.4 STEERING MODES
In Steering modes, the data input can be steered to any
or all of the four CWG output pins. In Synchronous
Steering mode, changes to steering selection registers
take effect on the next rising input.
In Non-Synchronous mode, steering takes effect on the
next instruction cycle. Additional details are provided in
Section 20.9 “CWG Steering Mode”.
FIGURE 20-4:
SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES)
Rev. 10-000164B
8/26/2015
See
CWGxISM
Register
CWGxISM <3:0>
D
Q
ERQ
EN
SHUTDOWN
20.2 Clock Source
The CWG module allows the following clock sources to
be selected:
• Fosc (system clock)
• HFINTOSC (16 MHz only)
The clock sources are selected using the CS bit of the
CWGxCLKCON register.
CWG_data
CWG_dataA
CWG_dataB
CWG_dataC
CWG_dataD
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 295