PIC16LF18854 Datasheet, PDF (439/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

FIGURE 29-13: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM (MODE = 10110)
MODE
TMR2_clk
PRx
Instruction⁽¹⁾
BS F
ON
TMR2_ers
TMRx
0
12345
TMR2_postscaled
0b10110
5
BS F
0
123
0
PWM Duty
Cycle
‘D3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
BCF BSF
12
3
Rev. 10-000 204A
5/30/201 4
450