PIC16LF18854 Datasheet, PDF (455/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 30-2: CCPxCAP: CAPTURE INPUT SELECTION REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-0/x
—
—
—
—
—
bit 7
R/W-0/x
CTS<2:0>
R/W-0/x
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
CTS<2:0>: Capture Trigger Input Selection bits
CTS
111
110
101
100
011
010
001
000
CCP1.capture
CCP1PPS
CCP2.capture
CCP2PPS
CCP3.capture
LC4_out
LC3_out
LC2_out
LC1_out
IOC_interrupt
C2OUT
C1OUT
CCP3PPS
CCP4.capture
CCP4PPS
CCP5.capture
CCP5PPS
REGISTER 30-3: CCPRxL REGISTER: CCPx REGISTER LOW BYTE
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
CCPRx<7:0>
bit 7
R/W-x/x
R/W-x/x
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
bit 7-0
CCPxMODE = Capture mode
CCPRxL<7:0>: Capture value of TMR1L
CCPxMODE = Compare mode
CCPRxL<7:0>: LS Byte compared to TMR1L
CCPxMODE = PWM modes when CCPxFMT = 0:
CCPRxL<7:0>: Pulse-width Least Significant eight bits
CCPxMODE = PWM modes when CCPxFMT = 1:
CCPRxL<7:6>: Pulse-width Least Significant two bits
CCPRxL<5:0>: Not used.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 455