PIC16LF18854 Datasheet, PDF (133/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-2: PIE0: PERIPHERAL INTERRUPT ENABLE REGISTER 0
U-0
U-0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
—
—
TMR0IE
IOCIE
—
—
—
bit 7
R/W-0/0
INTE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-6
bit 5
bit 4
bit 3-1
bit 0
Unimplemented: Read as ‘0’
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
IOCIE: Interrupt-on-Change Interrupt Enable bit
1 = Enables the IOC change interrupt
0 = Disables the IOC change interrupt
Unimplemented: Read as ‘0’
INTE: INT External Interrupt Flag bit⁽¹⁾
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
Note 1: The External Interrupt GPIO pin is selected by INTPPS (Register 13-1).
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt
controlled by PIE1-PIE8. Interrupt sources
controlled by the PIE0 register do not
require PEIE to be set in order to allow
interrupt vectoring (when GIE is set).
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 133