PIC16LF18854 Datasheet, PDF (139/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
REGISTER 7-8:
U-0
—
bit 7
PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
CCP5IE
CCP4IE
CCP3IE
R/W-0/0
CCP2IE
R/W-0/0
CCP1IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Hardware set
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’.
CCP5IE: CCP5 Interrupt Enable bit
1 = CCP5 interrupt is enabled
0 = CCP5 interrupt is disabled
CCP4IE: CCP4 Interrupt Enable bit
1 = CCP4 interrupt is enabled
0 = CCP4 interrupt is disabled
CCP3IE: CCP3 Interrupt Enable bit
1 = CCP3 interrupt is enabled
0 = CCP3 interrupt is disabled
CCP2IE: CCP2 Interrupt Enable bit
1 = CCP2 interrupt is enabled
0 = CCP2 interrupt is disabled
CCP1IE: CCP1 Interrupt Enable bit
1 = CCP1 interrupt is enabled
0 = CCP1 interrupt is disabled
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt
controlled by registers PIE1-PIE8.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 139