PIC16LF18854 Datasheet, PDF (512/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
32.1 SMT Operation
The core of the module is the 24-bit counter, SMTxTMR
combined with a complex data acquisition front-end.
Depending on the mode of operation selected, the SMT
can perform a variety of measurements summarized in
Table 32-1.
32.1.1 CLOCK SOURCES
Clock sources available to the SMT include:
• FOSC
• FOSC/4
• HFINTOSC 16 MHz
• LFINTOSC
• MFINTOSC 31.25 kHz
The SMT clock source is selected by configuring the
CSEL<2:0> bits in the SMTxCLK register. The clock
source can also be prescaled using the PS<1:0> bits of
the SMTxCON0 register. The prescaled clock source is
used to clock both the counter and any synchronization
logic used by the module.
32.1.2 PERIOD MATCH INTERRUPT
Similar to other timers, the SMT triggers an interrupt
when SMTxTMR rolls over to ‘0’. This happens when
SMTxTMR = SMTxPR, regardless of mode. Hence, in
any mode that relies on an external signal or a window
to reset the timer, proper operation requires that
SMTxPR be set to a period larger than that of the
expected signal or window.
32.2 Basic Timer Function Registers
The SMTxTMR time base and the
SMTxCPW/SMTxPR/SMTxCPR buffer registers serve
several functions and can be manually updated using
software.
32.2.1 TIME BASE
The SMTxTMR is the 24-bit counter that is the center of
the SMT. It is used as the basic counter/timer for
measurement in each of the modes of the SMT. It can be
reset to a value of 24’h00_0000 by setting the RST bit of
the SMTxSTAT register. It can be written to and read
from software, but it is not guarded for atomic access,
therefore reads and writes to the SMTxTMR should only
be made when the GO = 0, or the software should have
other measures to ensure integrity of SMTxTMR
reads/writes.
32.2.2 PULSE WIDTH LATCH REGISTERS
The SMTxCPW registers are the 24-bit SMT pulse
width latch. They are used to latch in the value of the
SMTxTMR when triggered by various signals, which
are determined by the mode the SMT is currently in.
The SMTxCPW registers can also be updated with the
current value of the SMTxTMR value by setting the
CPWUP bit of the SMTxSTAT register.
32.2.3 PERIOD LATCH REGISTERS
The SMTxCPR registers are the 24-bit SMT period
latch. They are used to latch in other values of the
SMTxTMR when triggered by various other signals,
which are determined by the mode the SMT is currently
in.
The SMTxCPR registers can also be updated with the
current value of the SMTxTMR value by setting the
CPRU bit in the SMTxSTAT register.
32.3 Halt Operation
The counter can be prevented from rolling-over using
the STP bit in the SMTxCON0 register. When halting is
enabled, the period match interrupt persists until the
SMTxTMR is reset (either by a manual reset, Section
32.2.1 “Time Base”) or by clearing the SMTxGO bit of
the SMTxCON1 register and writing the SMTxTMR
values in software.
32.4 Polarity Control
The three input signals for the SMT have polarity
control to determine whether or not they are active
high/positive edge or active low/negative edge signals.
The following bits apply to Polarity Control:
• WSEL bit (Window Polarity)
• SSEL bit (Signal Polarity)
• CSEL bit (Clock Polarity)
These bits are located in the SMTxCON0 register.
32.5 Status Information
The SMT provides input status information for the user
without requiring the need to deal with the polarity of
the incoming signals.
32.5.1 WINDOW STATUS
Window status is determined by the WS bit of the
SMTxSTAT register. This bit is only used in Windowed
Measure, Gated Counter and Gated Window Measure
modes, and is only valid when TS = 1, and will be
delayed in time by synchronizer delays in non-Counter
modes.
32.5.2 SIGNAL STATUS
Signal status is determined by the AS bit of the
SMTxSTAT register. This bit is used in all modes except
Window Measure, Time of Flight and Capture modes,
and is only valid when TS = 1, and will be delayed in
time by synchronizer delays in non-Counter modes.
DS40001824A-page 512
Preliminary
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