PIC16LF18854 Datasheet, PDF (25/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
TABLE 1-2: PIC16F18856 PINOUT DESCRIPTION (CONTINUED)
OUT⁽²⁾
Name
Function
CWG3C
Input
Type
—
Output Type
Description
CMOS/OD
Complementary Waveform Generator 3 output C.
CWG3D
—
CMOS/OD
Complementary Waveform Generator 3 output D.
CLC1OUT
—
CMOS/OD Configurable Logic Cell 1 output.
CLC2OUT
—
CMOS/OD Configurable Logic Cell 2 output.
CLC3OUT
—
CMOS/OD Configurable Logic Cell 3 output.
CLC4OUT
—
CMOS/OD Configurable Logic Cell 4 output.
NCO1
—
CMOS/OD Numerically Controller Oscillator output.
CLKR
—
CMOS/OD
Clock Reference module output.
Legend: AN = Analog input or output
TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
OD = Open-Drain
I²C = Schmitt Trigger input with I²C
HV = High Voltage
XTAL = Crystal levels
Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx
pins. Refer to Table 13-1 for details on which PORT pins may be used for this signal.
2: All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options
as described in Table 13-3.
3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and
PPS output registers.
4: These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS
assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,
instead of the I²C specific or SMBus input buffer thresholds.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 25