PIC16LF18854 Datasheet, PDF (251/668 Pages) Microchip Technology – C Compiler Optimized RISC Architecture

PIC16(L)F18856/76
14.0 PERIPHERAL MODULE
DISABLE
The PIC16F18855/75 provides the ability to disable
selected modules, placing them into the lowest
possible Power mode.
For legacy reasons, all modules are ON by default
following any Reset.
14.1 Disabling a Module
Disabling a module has the following effects:
• All clock and control inputs to the module are
suspended; there are no logic transitions, and the
module will not function.
• The module is held in Reset.
• Any SFRs become “unimplemented”
- Writing is disabled
- Reading returns 00h
• Module outputs are disabled; I/O goes to the next
module according to pin priority
14.2 Enabling a module
When the register bit is cleared, the module is re-
enabled and will be in its Reset state; SFR data will
reflect the POR Reset values.
Depending on the module, it may take up to one full
instruction cycle for the module to become active.
There should be no interaction with the module
(e.g., writing to registers) for at least one instruction
after it has been re-enabled.
14.3 Disabling a Module
When a module is disabled, any and all associated
input selection registers (ISMs) are also disabled.
14.4 System Clock Disable
Setting SYSCMD (PMD0, Register 14-1) disables the
system clock (FOSC) distribution network to the
peripherals. Not all peripherals make use of SYSCLK,
so not all peripherals are affected. Refer to the specific
peripheral description to see if it will be affected by this
bit.
 2016 Microchip Technology Inc.
Preliminary
DS40001824A-page 251